@Morgan Work though Verilog and VHDL posts a few months. You will not believe what you encounter. 30% are plain syntax errors which people can't find. 40% are about blocking vs non-blocking, 15% are code written like C ('how do I call a module'). 13% are weird loops which are not static. 2% are good questions.
VHDL Code for 4-bit Adder / Subtractor January 10, 2018 August 2, 2014 by shahul akthar This example describes a two input 4-bit adder/subtractor design in VHDL.
I would love to write a pages where people are referred to with every HDL question saying: Check these rules. If you break any of them correct and comes back if it still does not work. – May 3 '18 at 19:10.
The output of the adder drives the signal outputsignal but your register also drives the same signal. Changing one of them should help. For example change the adder output to feed the register input and the register output to feed the adder input. Ad: addersub4bits port map( a=outputsignal,b='0001', y=a,s=s); You can now choose if you use the register output outputsignal (good coding style) or the adder output a as output of upDown. Optional Tip1: When using the unresolved type stdulogic instead of stdlogic then a vhdl compiler must complain about a unresolved signal driven by multiple sources. So it is possible to find this kind of problems faster, even before the simulation starts. The disadvantage is that there is no IEEE.STD U LOGICUNSIGNED package in the VHDL standard.
![Using Using](http://3.bp.blogspot.com/-yvGF-5lU4Uw/UeVF_zvDAFI/AAAAAAAAAnU/6vM6BFCf5Sw/s1600/img7-16-2013-6.34.21+PM.jpg)
Optional Tip2: The package ieee.numericstd should be preferred instead of ieee.stdlogicarith which has some known problems. Putting both tips together an add/sub can still be written like this: if s='1' then y.